BLUENRG-1 datasheet(52/173 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-1

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3.8.2.6

Receive interrupt

The receive interrupt is asserted when the number of data in receive FIFO reaches the

programmed trigger watermark level. The receive interrupt is cleared by reading data from

the receive FIFO until there are less data than the programmed watermark level.

3.8.2.7

Transmit interrupt

The transmit interrupt is asserted when the number of data in the transmit FIFO is less than

or equal to the programmed watermark level. It is cleared by performing writes to the

transmit FIFO until it holds more elements than the programmed watermark level. The

transmitter interrupt is not qualified with the SPI enable bit, which allows operation in one of

two ways:



Data can be written to the transmit FIFO prior to enabling the SPI and the interrupts.



Or the SPI and the interrupts can be enabled so that data can be written to the

transmit FIFO by an interrupt service routine.

3.8.2.8

Timeout interrupt

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no

further data is received over a 32-bit period of the serial clock. This mechanism ensures

that the user is aware that data is still present in the receive FIFO and requires servicing.

The receive timeout interrupt is cleared either when the FIFO becomes empty through

reading all the data, or if new data is received, or when a 1b is written to the corresponding

bit of the ICR register.

3.8.2.9

Receive overrun interrupt

The receive overrun interrupt is asserted when the receive FIFO is already full and an

additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the

receive shift register, but not in the FIFO. The interrupt is cleared when a 1b is written to

the corresponding bit of the ICR register. This interrupt can never occur if hardware flow

control is enabled in the CR1 register.

3.8.2.10

Transmit underrun interrupt

The transmit underrun interrupt is asserted when the transmit FIFO is already empty and

an additional frame is transmitted, causing an underrun of the FIFO. Data is over-read in

the transmit shift register. This interrupt is cleared when a 1b is written to the corresponding

bit of the ICR register.

3.8.2.11

Transmit empty interrupt

The transmit interrupt is asserted when the transmit FIFO is empty. It is cleared by

performing writes to the transmit FIFO.

3.8.2.12

SPI Master communication mode

The SPIM register field selects the SPI transmission mode, these modes are applicable

only for SPI master mode:



Full duplex mode (SPIM = 00b): the master transmits the data available in the TXFIFO

and receives the data from the slave.



Transmit mode (SPIM = 01b): when the data is available in TX FIFO, the SPI_TX line

is run, and no data is written in RX FIFO



Receive mode (SPIM = 10b): the sequence of receive mode is:When the receive

mode is selected we have two cases:

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