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BLUENRG-1 Datasheet(PDF) 25 Page - STMicroelectronics |
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BLUENRG-1 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 173 page  BlueNRG-1 Functional details DocID028866 Rev 1 25/173 Table 15: CKGEN_SOC - DMA_CONFIG register description: address offset CKGEN_SOC_BASE_ADDR+0x24 Bit Field name Reset RW Description 0 ADC_CH0 0x0 RW Select ADC on DMA channel 0 instead of peripheral 1 ADC_CH1 0x0 RW Select ADC on DMA channel 1 instead of peripheral 2 ADC_CH2 0x0 RW Select ADC on DMA channel 2 instead of peripheral 3 ADC_CH3 0x0 RW Select ADC on DMA channel 3 instead of peripheral 4 ADC_CH4 0x0 RW Select ADC on DMA channel 4 instead of peripheral 5 ADC_CH5 0x0 RW Select ADC on DMA channel 5 instead of peripheral 6 ADC_CH6 0x0 RW Select ADC on DMA channel 6 instead of peripheral 7 ADC_CH7 0x0 RW Select ADC on DMA channel 7 instead of peripheral 31:8 RESERVED 0x0 R RESERVED Only one DMA channel for the ADC should be selected at time. Hardware does not prevent to select more than one DMA channel for ADC. CKGEN_BLE peripheral base address (CKGEN_BLE_BASE_ADDR) 0x48100000. Table 16: CKGEN_BLE registers Address offset Name RW Reset Description 0x08 REASON_RST R 0x00000005 Indicates the Reset reason from BLE. Refer to the detailed description below. 0x0C CLK32K_COUNT RW 0x0000000F Counter of 32 kHz clock. Refer to the detailed description below. 0x10 CLK32K_PERIOD R 0x00000000 Period of 32 kHz clock. Refer to the detailed description below. 0x14 CLK32K_FREQ R 0x00000000 Measurement of frequency of 32 kHz clock. Refer to the detailed description below. 0x18 CLK32K_IT RW 0x00000000 Interrupt event for 32 kHz clock measurement. Refer to the detailed description below. Table 17: CKGEN_BLE - REASON_RST register description: address offset CKGEN_BLE_BASE_ADDR+0x08 Bit Field name Reset RW Description 0 RESERVED 0x1 R RESERVED 1 BOR 0x0 R Reset from BOR 2 POR 0x1 R Reset from POR 3 WKP_IO9 0x0 R Wakeup from external IO9 4 WKP_IO10 0x0 R Wakeup from external IO10 5 WKP_IO11 0x0 R Wakeup from external IO11 |
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