BLUENRG-1 datasheet(91/173 Pages) STMICROELECTRONICS

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BlueNRG-1

Functional details

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Table 97: I2C - RFR register description: address offset I2CX_BASE_ADDR+0x18

Bit

Field name

Reset

Description

7:0

RDATA

0x0

Receive data. RDATA contains the received payload, related to

a master read or write-to-slave operation, to be read from the

Rx FIFO. The RDATA(0) is the first LSB bit received over the

I2C line. In case the FIFO is full, the I2C controller stretches

automatically the I2C clock line until a new entry is available.

For a write-to-slave operation, when the slave is addressed, the

interrupt I2C_RISR:WTSR bit is asserted for notification to the

CPU. In CPU mode the FIFO management shall be based on

the assertion of the interrupt bit I2C_RISR:RXFNF, related to

the nearly-full threshold.

In DMA mode, the single requests are automatically executed

based on the number of entries contained in the Rx FIFO.

31:8

RESERVED

0x0

RESERVED

Table 98: I2C - TFTR register description: address offset I2CX_BASE_ADDR+0x1C

Bit

Field name

Reset

Description

9:0

THRESH_TX

0x0

Threshold TX, contains the threshold value, in terms of

number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal

than the threshold value, the interrupt bit I2C_RISR:TXFNE is

set in order to request the loading of data to the application.

31:10

RESERVED

0x0

RESERVED

Table 99: I2C - RFTR register description: address offset I2CX_BASE_ADDR+0x20

Bit

Field name

Reset

Description

9:0

THRESH_RX

0x0

Threshold RX, contains the threshold value, in terms of

number of bytes, of the Rx FIFO.

When the number of entries of the RX FIFO is greater than

or equal to the threshold value, the interrupt bit RISR:RXFNF

is set in order to request the download of received data to the

application. The application shall download the received data

based on the threshold. (RISR:RXFNF).

31:10

RESERVED

0x0

RESERVED

Table 100: I2C - DMAR register description: address offset I2CX_BASE_ADDR+0x24

Bit

Field name

Reset

Description

7:0

RESERVED

0x0

RESERVED

10:8

DBSIZE_TX

0x0

Destination burst size. This register field is valid only if the

BURST_TX bit is set to '1'. If burst size is smaller than the

transaction length, only single request are generated.

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