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LAN91C111 Datasheet(PDF) 7 Page - Microchip Technology |
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LAN91C111 Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 125 page  2011-2016 Microchip Technology Inc. DS00002276A-page 7 LAN91C111 3.0 BLOCK DIAGRAMS The diagram shown in Figure 3-1, "Basic Functional Block Diagram", describes the device basic functional blocks. The Microchip LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions. The optional Serial EEPROM is used to store information relating to default IO offset parameters as well as which of the Interrupt line are used by the host. FIGURE 3-1: BASIC FUNCTIONAL BLOCK DIAGRAM PHY Core Ethernet MAC LAN91C111 Internal IEEE 802.3 MII (Media Independent Interface) Serial EEProm (Optional) ISA,Embedded Processor Transformer RJ45 Minimal LAN91C111 Configuration TX/RX Buffer (8K) |
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