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LAN91C111 Datasheet(PDF) 9 Page - Microchip Technology |
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LAN91C111 Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 125 page  2011-2016 Microchip Technology Inc. DS00002276A-page 9 LAN91C111 FIGURE 3-3: LAN91C111 PHYSICAL LAYER TO INTERNAL MAC BLOCK DIAGRAM COLLISION 4B5B DECODER DESCRAMBL ER CLOCK & DATA RECOVERY AUTO NEGOTIATION & LINK SQUELCH CLOCK & DATA Recovery (Manchester Decoder) LP FILTER ROM DAC + - 10BASE-T TRANSMITTER CLOCK GEN (PLL) MANCHESTER 4B5B ENCODER SCRAMBLER TPO+ SWITCHED CURRENT SOURCE + - 100BASE-TX TRANSMITTER CLOCK GEN (PLL) TPO- LP FILTER TPI+ TPI- LP FILTER +/- Vth 10BASE-T RECEIVER MLT3 ENCODER ADAPTIVE EQUALIZER +/- Vth 100BASE-TX RECEIVER MLT ENCODER SQUELCH RBIAS S 1 S 8 D C 1 EN B C 3 C 2 Multiplexer S 1 S 8 D C 1 EN B C 3 C 2 LS[2-0]B LEDA LEDB nPLED[0-5] LS[2-0]A LED Control Power On Reset PHY CONTROLS TXD[3:0] TX_ER TXEN100 TX25 CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 MCLK MDO MII AUTONEG LOGIC EEPROM CONTROL MDI MII SERIAL Manage -ment MII External Signals Multiplexer |
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