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LAN91C111 Datasheet(PDF) 8 Page - Microchip Technology |
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LAN91C111 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 125 page  LAN91C111 DS00002276A-page 8 2011-2016 Microchip Technology Inc. The diagram shown in Figure 3-2 describes the supported Host interfaces, which include ISA or Generic Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors. The figure shown next page describes the Microchip LAN91C111 functional blocks required to integrate a 10/100 Ether- net Physical layer framer to the internal MAC. FIGURE 3-2: BLOCK DIAGRAM 8-32 bit Bus Interface Unit Arbiter DMA MMU Ethernet Protocol Handler (EPH) 10/100 PHY 8K Byte Dynamically Allocated SRAM WR FIFO RD FIFO Control RX Data TX Data Control Control MII Address Data Control Control RXD[0-3] TXD[0-3] Control TX/RX FIFO Pointer TPI TPO Control EEPROM INTERFACE 32-bit Data 32-bit Data |
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