LAN91C111 datasheet(78/125 Pages) MICROCHIP

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DS00002276A-page 79

LAN91C111

10.3

Typical Flow of Events for Transmit (Auto Release = 1)

Upon transmit completion the first word in memory is

written with the status word. The packet number is

moved from the TX FIFO into the TX completion

FIFO. Interrupt is generated by the TX completion

FIFO being not empty.

If a TX failure occurs on any packets, TX INT is

generated and TXENA is cleared, transmission

sequence stops. The packet number of the failure

packet is presented at the TX FIFO PORTS Register.

SERVICE INTERRUPT - Read Interrupt Status

Packet Number from the FIFO Ports Register. Write

the packet number into the Packet Number Register.

The corresponding status word is now readable from

memory. If status word shows successful

transmission, issue RELEASE packet number

command to free up the memory used by this packet.

Remove packet number from completion FIFO by

writing TX INT Acknowledge Register.

Option 1) Release the packet.

Option 2) Check the transmit status in the EPH

STATUS Register, write the packet number of the

current packet to the Packet Number Register, re-

enable TXENA, then go to step 4 to start the TX

sequence again.

S/W Driver

MAC Side

ISSUE ALLOCATE MEMORY FOR TX - N BYTES -

the MMU attempts to allocate N bytes of RAM.

WAIT FOR SUCCESSFUL COMPLETION CODE -

Poll until the ALLOC INT bit is set or enable its mask

bit and wait for the interrupt. The TX packet number

is now at the Allocation Result Register.

LOAD TRANSMIT DATA - Copy the TX packet

number into the Packet Number Register. Write the

Pointer Register, then use a block move operation

from the upper layer transmit queue into the Data

ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"

- This command writes the number present in the

Packet Number Register into the TX FIFO. The

transmission is now enqueued. No further CPU

intervention is needed until a transmit interrupt is

generated.

The enqueued packet will be transferred to the MAC

block as a function of TXENA (nTCR) bit and of the

deferral process (1/2 duplex mode only) state.

Transmit pages are released by transmit completion.

The MAC generates a TXEMPTY interrupt upon a

completion of a sequence of enqueued packets.

If a TX failure occurs on any packets, TX INT is

generated and TXENA is cleared, transmission

sequence stops. The packet number of the failure

packet is presented at the TX FIFO PORTS Register.

S/W Driver

MAC Side

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