MB95F613K datasheet(53/110 Pages) CYPRESS

53 / 110 page

Document Number: 002-04698 Rev. *A

Page 53 of 110

PRELIMINARY

MB95610H Series

■ P36/SEG42/EC1 pin

This pin has the following peripheral functions:

❐ LCDC SEG42 output pin (SEG42)

❐ 8/16-bit composite timer ch. 1 clock input pin (EC1)

■ Block diagram of P36/SEG42/EC1

15.4.3 Port 3 registers

■ Port 3 register functions

■ Correspondence between registers and pins for port 3

15.4.4 Port 3 operations

■ Operation as an output port

❐ A pin becomes an output port if the bit in the DDR3 register corresponding to that pin is set to “1”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ When a pin is used as an output port, it outputs the value of the PDR3 register to external pins.

❐ If data is written to the PDR3 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

❐ Reading the PDR3 register returns the PDR3 register value.

abbreviation

Data

Read

Read by read-modify-write

(RMW) instruction

Write

PDR3

Pin state is “L” level.

PDR3 value is “0”.

As output port, outputs “L” level.

Pin state is “H” level.

PDR3 value is “1”.

As output port, outputs “H” level.

DDR3

Port input enabled

Port output enabled

Correspondence between related register bits and pins

Pin name

P37

P36

P35

P34

P33

P32

P31

P30

PDR3

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DDR3

PDR3

PDR3 read

PDR3 write

Executing bit manipulation instruction

DDR3 read

DDR3 write

DDR3

Stop mode, watch mode (SPL = 1)

Peripheral function input

Peripheral function input enable

LCD output

LCD output enable

MB95F613K Datasheet(PDF) 53 Page - Cypress Semiconductor

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