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MB95F613K Datasheet(PDF) 89 Page - Cypress Semiconductor |
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MB95F613K Datasheet(HTML) 89 Page - Cypress Semiconductor |
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89 / 110 page  Document Number: 002-04698 Rev. *A Page 89 of 110 PRELIMINARY MB95610H Series FCH (Main oscillation clock) Divided by 2 Divided by 2 Divided by 2 FMCRPLL (Main PLL clock, main CR PLL clock) FCRH (Main CR clock) FCL (Suboscillation clock) FCRL (Sub-CR clock) SCLK (Source clock) MCLK (Machine clock) Machine clock divide ratio select bits (SYCC:DIV[1:0]) Clock mode select bits (SYCC:SCS[2:0]) Division circuit × × × × 1 1/4 1/8 1/16 • Schematic diagram of the clock generation block A/D converter operation range 5.5 5.0 4.0 3.5 3.0 2.7 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) • Operating voltage - Operating frequency (TA = 40 °C to 85 °C) |
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