MB95F613K datasheet(59/110 Pages) CYPRESS

59 / 110 page

Document Number: 002-04698 Rev. *A

Page 59 of 110

PRELIMINARY

MB95610H Series

■ Operation in stop mode and watch mode

❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR5 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P51/EC0 is

enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit

control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.

❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

■ Operation of the pull-up register

Setting the bit in the PUL5 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,

the pull-up resistor is disconnected regardless of the value of the PUL5 register.

MB95F613K Datasheet(PDF) 59 Page - Cypress Semiconductor