MB95F613K datasheet(62/110 Pages) CYPRESS

62 / 110 page

Document Number: 002-04698 Rev. *A

Page 62 of 110

PRELIMINARY

MB95610H Series

15.6.4 Port 9 operations

■ Operation as an output port

❐ A pin becomes an output port if the bit in the DDR9 register corresponding to that pin is set to “1”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ When a pin is used as an output port, it outputs the value of the PDR9 register to external pins.

❐ If data is written to the PDR9 register, the value is stored in the output latch and is output to the pin set as an output port as it is.

❐ Reading the PDR9 register returns the PDR9 register value.

❐ To use a pin shared with the LCDC as an output port, set the bit corresponding to that pin in the VE[4:0] bits in the LCDC enable

■ Operation as an input port

❐ A pin becomes an input port if the bit in the DDR9 register corresponding to that pin is set to “0”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ If data is written to the PDR9 register, the value is stored in the output latch but is not output to the pin set as an input port.

❐ Reading the PDR9 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the

PDR9 register, the PDR9 register value is returned.

❐ To use a pin shared with the LCDC as an input port, set the bit (VE[4:0]) corresponding to that pin in the LCDCE1 register to “0”.

■ Operation at reset

If the CPU is reset, all bits in the DDR9 register are initialized to “0” and port input is enabled.

■ Operation in stop mode and watch mode

❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR9 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open.

❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

■ Operation as an LCDC drive power supply pin

❐ Set the bit in the DDR9 register corresponding to a desired LCDC drive power supply pin to “0”.

❐ Select the LCDC drive power supply pin by setting the bit corresponding to that pin in the VE[4:0] bits in the LCDCE1 register to “1”.

MB95F613K Datasheet(PDF) 62 Page - Cypress Semiconductor