MB95F613K datasheet(95/110 Pages) CYPRESS

95 / 110 page

Document Number: 002-04698 Rev. *A

Page 95 of 110

PRELIMINARY

MB95610H Series

(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)

Parameter

Symbol

name

Condition

Value*2

Unit

Remarks

Min

Max

SCL clock “L”

width

tLOW

SCL

R = 1.7 k

,

C = 50 pF*1

 nm/2)tMCLK  20

—

Master mode

SCL clock “H”

width

tHIGH

SCL

(nm/2)tMCLK  20

(nm/2)tMCLK  20

Master mode

START

condition hold

time

tHD;STA

SCL,

SDA

(-1

 nm/2)tMCLK  20

(-1

 nm)tMCLK  20

Master mode

Maximum value is applied when

m, n = 1, 8.

Otherwise, the minimum value is

applied.

STOP condition

setup time

tSU;STO

SCL,

SDA

 nm/2)tMCLK  20

 nm/2)tMCLK  20

Master mode

START

condition setup

time

tSU;STA

SCL,

SDA

 nm/2)tMCLK  20

 nm/2)tMCLK  20

Master mode

Bus free time

between STOP

condition and

START

condition

tBUF

SCL,

SDA

(2 nm

 4) tMCLK  20

—

Data hold time

tHD;DAT

SCL,

SDA

3 tMCLK  20

—

Master mode

Data setup time

tSU;DAT

SCL,

SDA

(-2

 nm/2) tMCLK  20

(-1

 nm/2) tMCLK  20

Master mode

It is assumed that “L” of SCL is

not extended. The minimum

value is applied to the first bit of

continuous data. Otherwise, the

maximum value is applied.

Setup time

between

clearing

interrupt and

SCL rising

tSU;INT SCL

(nm/2) tMCLK  20

 nm/2) tMCLK  20

The minimum value is applied to

the interrupt at the ninth SCL

.

The maximum value is applied to

the interrupt at the eighth SCL

.

SCL clock “L”

width

tLOW

SCL

4 tMCLK  20

—

At reception

SCL clock “H”

width

tHIGH

SCL

4 tMCLK  20

—

At reception

SDA

SCL

tWAKEUP

tHD;STA

tSU;DAT

fSCL

tHD;STA

tSU;STA

tLOW

tHD;DAT

tHIGH

tSU;STO

tBUF

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