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MB95F613K Datasheet(PDF) 97 Page - Cypress Semiconductor

Part # MB95F613K
Description  F2MC-8FX CPU core
PDF  110 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F613K Datasheet(HTML) 97 Page - Cypress Semiconductor

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Document Number: 002-04698 Rev. *A
Page 97 of 110
PRELIMINARY
MB95610H Series
18.4.8 UART/SIO, Serial I/O Timing
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
*: See “Source Clock/Machine Clock” for tMCLK.
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
UCK0, UCK1
Internal clock operation:
CL = 80 pF + 1 TTL
4 tMCLK*—
ns
UCK
 UO time
tSLOV
UCK0, UCK1, UO0,
UO1
190
190
ns
Valid UI
 UCK 
tIVSH
UCK0, UCK1, UI0,
UI1
2 tMCLK*—
ns
UCK
 valid UI hold time
tSHIX
UCK0, UCK1, UI0,
UI1
2 tMCLK*—
ns
Serial clock “H” pulse width
tSHSL
UCK0, UCK1
External clock operation:
CL = 80 pF + 1 TTL
4 tMCLK*—
ns
Serial clock “L” pulse width
tSLSH
UCK0, UCK1
4 tMCLK*—
ns
UCK
 UO time
tSLOV
UCK0, UCK1, UO0,
UO1
—
190
ns
Valid UI
 UCK 
tIVSH
UCK0, UCK1, UI0,
UI1
2 tMCLK*—
ns
UCK
 valid UI hold time
tSHIX
UCK0, UCK1, UI0,
UI1
2 tMCLK*—
ns
0.2 VCC
0.2 VCC
0.8 VCC
tSLOV
tIVSH
tSHIX
0.8 VCC
0.2 VCC
UCK0,
UCK1
UO0,
UO1
UI0,
UI1
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
• Internal shift clock mode



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