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MB95F613K Datasheet(PDF) 88 Page - Cypress Semiconductor |
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MB95F613K Datasheet(HTML) 88 Page - Cypress Semiconductor |
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88 / 110 page  Document Number: 002-04698 Rev. *A Page 88 of 110 PRELIMINARY MB95610H Series 18.4.2 Source Clock/Machine Clock (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • PLL multiplication of main clock or main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.) • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 Parameter Symbol Pin name Value Unit Remarks Min Typ Max Source clock cycle time*1 tSCLK — 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 62.5 — 1000 ns When the main CR clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, divided by 4 —61— µs When the suboscillation clock is used FCL = 32.768 kHz, divided by 2 —20— µs When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Source clock frequency FSP — 0.5 — 16.25 MHz When the main oscillation clock is used — 4 12.5 MHz When the main CR clock is used FSPL — 16.384 — kHz When the suboscillation clock is used — 50 — kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Machine clock cycle time*2 (minimum instruction execution time) tMCLK — 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 250 — 4000 ns When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 16 61 — 976.5 µs When the suboscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 Machine clock frequency FMP — 0.031 — 16.25 MHz When the main oscillation clock is used 0.25 — 16 MHz When the main CR clock is used FMPL 1.024 — 16.384 kHz When the suboscillation clock is used 3.125 — 50 kHz When the sub-CR clock is used FCRL = 100 kHz |
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