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MB95F613K Datasheet(PDF) 30 Page - Cypress Semiconductor |
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MB95F613K Datasheet(HTML) 30 Page - Cypress Semiconductor |
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30 / 110 page  Document Number: 002-04698 Rev. *A Page 30 of 110 PRELIMINARY MB95610H Series (Continued) Address Register abbreviation Register name R/W Initial value 0x0062 IBSR0 I2C bus status register ch. 0 R/W 0b00000000 0x0063 IDDR0 I2C data register ch. 0 R/W 0b00000000 0x0064 IAAR0 I2C address register ch. 0 R/W 0b00000000 0x0065 ICCR0 I2C clock control register ch. 0 R/W 0b00000000 0x0066 to 0x006B — (Disabled) — — 0x006C ADC1 8/10-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter status register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — Mirror of register bank pointer (RP) and direct bank pointer (DP) — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — (Disabled) — — 0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000 0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — (Disabled) — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 |
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