MB95F613K datasheet(55/110 Pages) CYPRESS

55 / 110 page

Document Number: 002-04698 Rev. *A

Page 55 of 110

PRELIMINARY

MB95610H Series

■ Operation as an LCDC segment output pin

❐ Set the bit in the DDR3 register corresponding to a desired LCDC segment output pin to “0”.

❐ Select the segment pin by setting a corresponding function select bit in the LCDC enable register 8 (LCDCE8:SEG[43:40]) or in

the LCDC enable register 7 (LCDCE7:SEG[39:36]) to “1”, and then set the PICTL bit in the LCDCE1 register to “1”.

■ Operation at reset

If the CPU is reset, all bits in the DDR3 register are initialized to “0” and port input is enabled.

■ Operation in stop mode and watch mode

❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch

mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR3 register value. The input of that

pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the

external interrupt (INT04 to INT07), the input is enabled and not blocked.

❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output

level is maintained.

■ Operation as an external interrupt input pin

❐ Set the bit in the DDR3 register corresponding to the external interrupt input pin to “0”.

❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.

❐ The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the

external interrupt function corresponding to that pin.

MB95F613K Datasheet(PDF) 55 Page - Cypress Semiconductor