AD9542BCPZ datasheet(32/61 Pages) AD

32 / 61 page

AD9542

Data Sheet

Rev. 0 | Page 32 of 61

APPLICATIONS INFORMATION

OPTICAL NETWORKING LINE CARD

In this application (shown in Figure 41), the AD9542 is used in

a variety of ways.

In a loop timed (WAN) mode, one of the AD9542 DPLLs locks

to the CDR and is used to remove jitter on the receiver path,

sending that clock to the central timing card, as well as the

framer. In some applications, the AD9542 can also perform a

variety of frequency translation tasks, such as multiplying or

dividing by an FEC ratio, and/or removing jitter from a gapped

clock. The other DPLL cleans jitter and provides clocking to the

transmitter path.

Other tasks include frequency translation and jitter cleaning of

the reference clock from the timing card, as well as seamlessly

managing the reference switching from Timing Card A to

Timing Card B.

Given the continually evolving nature of optical line card

protocols and functions, the functions listed in this section are

by no means exhaustive.

FRAMER/FEC

DESERIALIZER

CDR

FRAMER/FEC

SERIALIZER

LDD

LASER DIODE

POST

AMP

TIA

PHOTO DIODE

LINE CARD

OPTICAL MODULE

TO SDH/PDH

OPTICAL

NETWORK

AD9542

FROM TIMING CARD B

FROM TIMING CARD A

Figure 41. Optical Line Card Example

AD9542BCPZ Datasheet(PDF) 32 Page - Analog Devices

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