AD9542BCPZ datasheet(51/61 Pages) AD

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Data Sheet

AD9542

Rev. 0 | Page 51 of 61

The previous procedure is an example of an upload sequence

consisting of two subsequences. Most upload sequences require

more than two subsequences; however, the procedure is the same.

Specifically, partition a long sequence into several subsequences

by using the pause instruction at the end of each subsequence

and the end of data instruction at the end of the final subsequence.

EEPROM Checksum

When the EEPROM controller encounters an end of data

instruction (see Table 31) during an upload sequence, it

computes a 32-bit cyclic redundancy check (CRC) checksum

and appends it to the stored data in the EEPROM. Similarly,

when the EEPROM controller executes a download sequence, it

computes a checksum on the fly. At the end of a download

sequence, the EEPROM controller compares the newly

computed checksum to the one stored in the EEPROM. If the

two checksums do not match, the EEPROM controller asserts

the EEPROM CRC error bit in the status readback section of

the register map.

To minimize the possibility of downloading a corrupted

EEPROM data set, the user can execute a checksum test by

asserting the verify EEPROM CRC bit in the EEPROM section

of the register map, which causes the EEPROM controller to

execute a download sequence, but without actually transferring

data to the AD9542 registers. The controller still computes an

on the fly checksum, performs the checksum comparison, and

asserts the EEPROM CRC error bit if the checksums do not

match. Therefore, after the device deasserts the EEPROM load

in progress bit, the user can check the EEPROM CRC fault bit

to determine if the test passed (that is, EEPROM CRC error = 0).

However, even if the test fails, device operation is unaffected

because there was no transfer of data to the AD9542 registers.

EEPROM Header

The EEPROM controller adds a header to stored data that

carries information related to the AD9542, such as

•

Vendor ID

•

Chip type

•

Product ID

•

Chip revision

At the beginning of an EEPROM download sequence, the

EEPROM controller compares the stored header values to the

values in the corresponding registers of the AD9542. If the

controller detects a mismatch, it asserts the EEPROM fault bit

in the status readback section of the register map and

terminates the download.

EEPROM INSTRUCTION SET

The EEPROM controller relies on a combination of instructions

and data. An instruction consists of a single byte (eight bits).

Some instructions require subsequent bytes of payload data.

That is, some instructions are self contained operations, whereas

others are directions on how to process subsequent payload

data. A summary of the EEPROM controller instructions is

shown in Table 31.

When the controller downloads the EEPROM contents to the

AD9542 registers, it does so in a linear fashion, stepping

through the instructions stored in the EEPROM. However, when

the controller uploads to the EEPROM, the sequence is a nonlinear

combination of various parts of the register map, as well as

computed data that the controller calculates on the fly.

Table 31. EEPROM Controller Instruction Set Summary

Instruction Code

(Hexadecimal)

Response

Comments

0x00 to 0x7F

Requires a 2-byte register address suffix

0x80

Input/output update

Assert input/output update during download

0x81 to 0x8F

Not applicable

Undefined

0x90

Calibrate APLLs

Calibrate the system clock PLL, APLL0, and APLL1 during download

0x91

Calibrate the system clock PLL

Calibrate only the system clock PLL during download

0x92

Calibrate APLL0

Calibrate only APLL0 during download

0x93

Calibrate APLL1

Calibrate only APLL1 during download

0x94 to 0x97

Not applicable

Reserved/unused

0x98

Force freerun

Force DPLL0 and DPLL1 to freerun during download

0x99

Force DPLL0 freerun

Force only DPLL0 to freerun during download

0x9A

Force DPLL1 freerun

Force only DPLL1 to freerun during download

0x9B to 0x9F

Not applicable

Reserved/unused

0xA0

Synchronize outputs

Synchronize all distribution outputs during download

0xA1

Synchronize Channel 0

Synchronize only Channel 0 distribution outputs during download

0xA2

Synchronize Channel 1

Synchronize only Channel 1 distribution outputs during download

0xA3 to 0xAF

Not applicable

Reserved/unused

0xB0

Clear condition

Apply Condition 0 and reset the condition map

0xB1 to 0xBF

Set condition

Apply Condition 1 to Condition 15, respectively

0xC0 to 0xFD

Not applicable

Undefined

0xFE

Pause

Pause the EEPROM upload sequence

0xFF

End of data

Marks the end of the instruction sequence

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