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AD9542BCPZ Datasheet(PDF) 11 Page - Analog Devices

Part # AD9542BCPZ
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542BCPZ Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD9542
Rev. 0 | Page 11 of 61
DIGITAL PLL LOCK DETECTION SPECIFICATIONS
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
10
224 − 1
ps
Threshold Resolution
1
ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
10
224 − 1
ps
Threshold Resolution
1
ps
PHASE STEP DETECTOR
Threshold Programming Range
100
232 − 1
ps
Setting this value too low causes false triggers
Threshold Resolution
1
ps
HOLDOVER SPECIFICATIONS
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy
±0.01
±0.1
ppb
AD9542 is configured using Configuration 1 from Table 21;
excludes frequency drift of system clock (SYSCLK) source;
excludes frequency drift of input reference prior to
entering holdover; 160 ms history timer; history holdoff
setting of 8; three holdover history features (bits) are
enabled: delay history until frequency lock bit, delay
history until phase lock bit, and delay holdover history
accumulation until not phase slew limited bit
Relative Frequency Accuracy
Between Channels
Cascaded Operation
0
ppb
History Averaging Window
0.001
268435
sec
ANALOG PLL (APLL0, APLL1) SPECIFICATIONS
Table 13.
Parameter
Min
Typ
Max
Unit
VCO FREQUENCY RANGE
Analog PLL0 (APLL0)
2424
3232
MHz
Analog PLL1 (APLL1)
3232
4040
MHz
PHASE FREQUENCY DETECTOR (PFD) INPUT FREQUENCY RANGE
162
350
MHz
LOOP BANDWIDTH
260
kHz
PHASE MARGIN
68
Degrees
OUTPUT CHANNEL DIVIDER SPECIFICATIONS
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT PHASE ADJUST STEP SIZE
1
t
VCO
t
VCO = 1/(APLLx VCO frequency), where x = 0, 1



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