AD9542BCPZ datasheet(48/61 Pages) AD

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AD9542

Data Sheet

Rev. 0 | Page 48 of 61

PHASE STEP DETECTOR

PHASE STEP LIMIT

Although the AD9542 has the ability to switch between multiple

reference inputs, some applications use only one input and handle

reference switching externally (see Figure 50). Unfortunately,

this arrangement forfeits the ability of the AD9542 to mitigate

the output disturbance associated with a reference switchover,

because the reference switchover is not under the control of the

AD9542. However, the AD9542 offers a phase transient threshold

detection feature to help identify when an external reference

switchover occurs and to act accordingly.

AD9542

REFx, REFxx

REFERENCE 1

REFERENCE 2

SWITCHOVER

CONTROL

Figure 50. External Reference Switching

Phase transient threshold detection works by monitoring the

output of the DPLL phase detector for phase transients, but in a

manner that is somewhat jitter tolerant. Otherwise, the phase

transient threshold detector is prone to false positives.

To activate the phase transient threshold detection, program the

32-bit unsigned Profile x phase step threshold bit field (where x

is a value from 0 through 7, corresponding to a particular

source profile). The default value is zero, which disables the phase

transient threshold detector. A nonzero value denotes the

desired phase step threshold in units of picoseconds per the

following equation:

Phase Step Threshold = Profile x Phase Step Threshol

d × 10−12

Note that the phase transient threshold detector is not active

unless the DPLL indicates frequency locked status.

As an example, determine the value of the Profile x phase step

threshold bit field necessary for a 12 ns limit. Solving the

previous equation for the phase step limit yields

Profile x Phase Step Threshold = (12 × 10

−9)/10−12

= 12,000

= 0x00002EE0 (hexadecimal)

To reduce the likelihood of jitter induced threshold violations,

choose a phase step threshold of at least two times the expected

rms jitter (σ

JITTER) associated with the input reference signal.

Profile x Phase Step Threshold ≥ 2 × σ

JITTER

As such, in the previous example with Profile x phase step

threshold = 12,000, an input signal with 12 ns rms jitter is likely

to produce false positives because the signal violates the

previously described inequality. To reduce the likelihood of a

false positive, the inequality indicates Profile x phase step

threshold = 24,000 is a better choice. In fact, even with a value

of 24,000, there is still a slight probability of a jitter sample

exceeding 2 × σ

JITTER. As such, scaling σJITTER by four to six is an

even better choice.

When a phase transient occurs that exceeds the prescribed

value, one or both of the following two events occurs,

depending on the state of the enable step detect reference fault

bit in the operational control Channel 0 and Channel 1 (DPLL0

and DPLL1) sections of the register map:

•

Logic 0: the DPLL initiates a new acquisition sequence.

•

Logic 1: the reference monitor is reset.

When the enable step detect reference fault bit is Logic 0

(default), detection of a phase step causes only the first event to

occur. By initializing a new DPLL acquisition sequence, the

DPLL can take advantage of the fast acquisition feature,

assuming it is active, which is especially helpful for very low loop

bandwidth applications. In addition, a new acquisition manages

the impact of the phase step by either building out the phase or

slewing to the new phase in a hitless manner.

When the enable step detect reference fault bit is Logic 1,

detection of a phase step causes both events to occur. Because

exceeding the phase step threshold in this case implies an

external switch to a new reference, resetting the reference

monitor forces it to establish new reference statics.

The phase transient threshold detector provides the user with a

live status bit in the status readback PLLx section of the register

map, as well as a latched status bit in the IRQ map DPLLx read

section of the register map. The DPLLx phase step detect bit

(where x is 0 or 1) latches to Logic 1 on threshold violation of

the phase transient threshold detector. Because this is a latched

bit, the user must clear it via the IRQ map DPLLx clear section

of the register map to obtain visibility of subsequent threshold

violations detected by the phase step detector.

Mitigating Phase Step Limit False Positives

When enabled, the phase transient threshold detector operates

continuously, as long as the associated reference is the active

reference for the DPLL (DPLL0 or DPLL1, assuming the DPLL

is frequency locked. As such, any phase disturbance at the input

to the phase detector of the DPLL is subject to violating the

threshold of the phase transient threshold detector. This

violation includes a user induced phase adjustment via the

DPLLx phase offset bit field or the Profile x phase skew bit field.

To mitigate false triggering of the phase transient threshold

detector (when enabled) due to intentional phase adjustments,

the user can employ the phase slew rate limiter DPLL.

The following formula relates the maximum phase slew rate

(MPSR) necessary to prevent inadvertent triggering of the

phase transient threshold detector:

MPSR = (P + F)/7

where:

P is the phase transient threshold detector limit (in

picoseconds).

F is the frequency (in Hz) at the input of the DPLL phase

detector.

AD9542BCPZ Datasheet(PDF) 48 Page - Analog Devices

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