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AD9542BCPZ Datasheet(PDF) 60 Page - Analog Devices

Part # AD9542BCPZ
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542BCPZ Datasheet(HTML) 60 Page - Analog Devices

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AD9542
Data Sheet
Rev. 0 | Page 60 of 61
Data Transfer Format
The write byte format is used to write a register address to the
RAM starting from the specified RAM address (see Table 38).
The send byte format is used to set up the register address for
subsequent reads (see Table 39). The receive byte format is used
to read the data byte(s) from RAM starting from the current
address (see Table 40). The read byte format is the combined
format of the send byte and the receive byte (see Table 41).
Table 38. Write Byte Format
S
Slave
address
WE
A
RAM address high byte
A
RAM address low byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Table 39. Send Byte Format
S
Slave address
WE
A
RAM address high byte
A
RAM address low byte
A
P
Table 40. Receive Byte Format
S
Slave address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
AE
P
Table 41. Read Byte Format
S
Slave
address
WE
A
RAM address
high byte
A
RAM address
low byte
A
Sr
Slave
address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
AE
P
I²C Serial Port Timing
S
Sr
S
P
SDA
SCL
tSP
tHD; STA
tSU; STA
tSU; DAT
tHD; DAT
tHD; STA
tSU; STO
tBUF
tR
tF
tR
tF
tHIGH
tLOW
Figure 64. I²C Serial Port Timing
Table 42. I2C Timing Definitions
Parameter
Description
fSCL
Serial clock
tBUF
Bus free time between stop and start conditions
tHD; STA
Repeated hold time start condition
tSU; STA
Repeated start condition setup time
tSU; STO
Stop condition setup time
tHD; DAT
Data hold time
tSU; DAT
Data setup time
tLOW
SCL clock low period
tHIGH
SCL clock high period
tR
Minimum/maximum receive SCL and SDA rise time
tF
Minimum/maximum receive SCL and SDA fall time
tSP
Pulse width of voltage spikes that must be suppressed by the input filter



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