AD9542BCPZ datasheet(8/61 Pages) AD

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AD9542

Data Sheet

Rev. 0 | Page 8 of 61

REFERENCE MONITORS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference

Detection Time

4.9 + 0.13 × t

PFD

µs

PFD is the nominal phase detector period, R/fREF, where R is

the frequency division factor determined by the R divider,

and f

REF is the frequency of the active reference

Frequency Out of

Range Limits

5 × 10−8

0.015

ppb

Parts per billion (ppb) is defined as Δf/f

REF, where Δf is the

frequency deviation, and f

REF is the reference input

frequency; programmable with the lower bound, subject

to quality of the system clock (or the source of system

clock compensation)

Validation Timer

0.001

1048

sec

Programmable in 1 ms increments

Excess Jitter Alarm Threshold

65535

Programmable in 1 ns increments

DPLL PHASE CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT PHASE

PERTURBATION

Assumes a jitter free reference; satisfies Telcordia GR-1244-CORE

requirements; 0 ppm frequency difference between references;

reference switch initiated via register map (see the AD9542 Register

Map Reference Manual) by faulting the active reference input

Phase Refinement Disabled

50 Hz DPLL loop bandwidth; normal phase margin mode; frequency

translation = 19.44 MHz to 155.52 MHz; 49.152 MHz signal generator

used for system clock source

Peak

±20

±140

Steady State

Phase Buildout Operation

±18

±125

Hitless Operation

Phase Refinement Enabled

50 Hz DPLL loop bandwidth; high phase margin mode; phase

refinement iterations = 4; frequency translation = 19.44 MHz to

155.52 MHz; 49.152 MHz signal generator used for system clock source

Peak

±5

±40

Steady State

Phase Buildout Operation

±4

±35

Hitless Operation

PHASE SLEW LIMITER

0.001

250

µs/sec

See the AN-1420 Application Note, Phase Buildout and Hitless

Switchover with Digital Phase-Locked Loops (DPLLs)

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