AD9542BCPZ datasheet(43/61 Pages) AD

43 / 61 page

Data Sheet

AD9542

Rev. 0 | Page 43 of 61

INTERRUPT REQUEST (IRQ)

The AD9542 monitors certain internal device events potentially

allowing them to trigger an IRQ event. Three groups of registers

(see Figure 47) control the IRQ functionality within the AD9542:

•

IRQ monitor registers (Register 0x300B through

•

IRQ mask registers (Register 0x10C through Register 0x11A)

•

IRQ clear registers (Register 0x2006 through Register 0x2014)

The IRQ logic can indicate an IRQ event status result for any

specific device event(s) via the logical OR of the status of all the

IRQ monitor bits. In addition, the IRQ logic offers IRQ event

status results for particular groups of specific IRQ events,

namely, the PLL0 IRQs, PLL1 IRQs, and common IRQs (see

Figure 47).

The PLL0 IRQ group includes all device events associated with

DPLL0 and APLL0. The PLL1 IRQ group includes all device

events associated with DPLL1 and APLL1. The common IRQ

group includes events associated with the system clock, the

watchdog timer, and the EEPROM.

IRQ MONITOR

The IRQ monitor registers (in the general status section of the

occurrence of a specific device event results in the setting and

latching of the corresponding bit in the IRQ monitor. The

output of the IRQ monitor provides the mechanism for

generating IRQ event status results (see the PLL0 IRQ, PLL1

IRQ, common IRQ, or any IRQ signal shown in Figure 47).

IRQ MASK

The IRQ mask registers (in the Mx pin status and control section

of the register map) comprise a bit for bit correspondence with

the specific IRQ event bits within the IRQ monitor. Writing a

Logic 1 to a mask bit enables (unmasks) the corresponding

specific device event to the IRQ monitor. A Logic 0 (default)

disables (masks) the corresponding specific device event to the

IRQ monitor. Therefore, a specific IRQ event is the result of a

logical AND of a specific device event and its associated IRQ,

mask bit.

The presence of the IRQ mask allows the user to select certain

device events for generating an IRQ event, while ignoring

(masking) all other specific device events from contributing to

an IRQ event status result (PLL0 IRQ, PLL1 IRQ, common IRQ

or any IRQ signal in Figure 47). Note that the default state of the

IRQ mask register bits is Logic 0; therefore, the device is not

capable of generating an IRQ event status result until the user

populates the IRQ mask with a Logic 1 to unmask the desired

specific IRQ events. Writing a Logic 1 to an IRQ mask bit may

result in immediate indication of an IRQ status event result if the

corresponding specific device event is already asserted (that is,

the device previously registered the corresponding device event).

IRQ CLEAR

The IRQ clear registers (in the operational controls section of

the register map) comprise a bit for bit correspondence with

the IRQ monitor. Writing a Logic 1 to an IRQ clear bit forces

the corresponding IRQ monitor bit to Logic 0, thereby clearing

that specific IRQ event. Note that the IRQ clear registers are

autoclearing; therefore, after writing a Logic 1 to an IRQ clear bit,

the device automatically restores the IRQ clear bit to Logic 0.

The IRQ event status results remain asserted until the user

clears all of the bits in the IRQ monitor responsible for the IRQ

status result (that is, the entire group of status bits associated

with PLL0 IRQ, PLL1 IRQ, common IRQ, or any IRQ signal

shown in Figure 47).

Although it is not recommended, in certain applications, it

may be desirable to clear an entire IRQ group all at one time.

Bit D0 clears all IRQ monitor bits. Bit D1 clears the common

IRQ bits. Bit D2 clears the PLL0 IRQ bits. Bit D3 clears the

PLL1 IRQ bits.

Alternately, the user can program any of the multifunction pins

as an input for clearing an IRQ group, which allows clearing an

IRQ group with an external logic signal rather than by writing

to Register 0x2005 (see Figure 47).

The recommendation for clearing IRQ status events is to first

service the specific IRQ event (as needed) and then clear the

specific IRQ for that particular IRQ event. Clearing IRQ groups

via Register 0x2005 or via an Mx pin requires great care.

Clearing an IRQ group all at one time may result in the

unintentional clearing of one or more asserted IRQ monitor

bits. Clearing asserted IRQ monitor bits eliminates the record of

the associated device events, subsequently erasing any history of

those events having occurred.

AD9542BCPZ Datasheet(PDF) 43 Page - Analog Devices

AD9542BCPZ Datasheet(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL