AD9542BCPZ datasheet(59/61 Pages) AD

Part #	AD9542BCPZ

Description	Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator

PDF	61 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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59 / 61 page

Data Sheet

AD9542

Rev. 0 | Page 59 of 61

nonacknowledge bit). By receiving the nonacknowledge bit, the

slave device knows that the data transfer is finished and enters

idle mode. The master device then takes the data line low

during the low period before the 10th clock pulse, and high

during the 10th clock pulse to assert a stop condition.

A start condition can be used instead of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

SDA

START CONDITION

STOP CONDITION

SCL

Figure 60. Start and Stop Conditions

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

Figure 61. Acknowledge Bit

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

3 TO 7

ACK FROM

MASTER RECEIVER

NONACK FROM

MASTER RECEIVER

SDA

SCL

Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave

AD9542BCPZ Datasheet(PDF) 59 Page - Analog Devices

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