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AD9542BCPZ Datasheet(PDF) 4 Page - Analog Devices

Part # AD9542BCPZ
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542BCPZ Datasheet(HTML) 4 Page - Analog Devices

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AD9542
Data Sheet
Rev. 0 | Page 4 of 61
FUNCTIONAL BLOCK DIAGRAM
AD9542
REFA
Mx PINS
SERIAL PORT
(OPTIONAL EXTERNAL EEPROM)
XOA
XOB
OUT0AP
OUT0AN
OUT0BP
OUT0BN
OUT0CP
OUT0CN
OUT1AP
OUT1AN
OUT1BP
OUT1BN
REFB
REFBB
REFAA
REF
DEMOD
REF
DEMOD
÷RA
÷RAA
TDC
TDC
REF
DEMOD
REF
DEMOD
÷RB
÷RBB
TDC
TDC
REFERENCE
MONITORS
REFERENCE
SWITCHING
AUXILIARY
NCOs
AUXILIARY
TDCs
STATUS AND
CONTROL PINS
EXTERNAL
EEPROM
(OPTIONAL)
SYSTEM
CLOCK PLL
TEMPERATURE
SENSOR
SYSTEM CLOCK
COMPENSATION
INTERNAL
ZERO DELAY
DPLL1
APLL1
SERIAL PORT
(SPI OR I2C)
CONTROLLER
3.232GHz
TO
4.04GHz
2.424GHz
TO
3.232GHz
DPLL0
APLL0
DIGITAL
CROSSPOINT
MUX
SYSTEM
CLOCK
÷Q0A
÷Q0AA
÷Q0B
÷Q0BB
÷Q0C
÷Q0CC
÷Q1A
÷Q1AA
÷Q1B
÷Q1BB
MODULATION, PHASE
OFFSET, AND JESD204B
Figure 1.



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