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AD9542BCPZ Datasheet(PDF) 35 Page - Analog Devices

Part # AD9542BCPZ
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542BCPZ Datasheet(HTML) 35 Page - Analog Devices

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Data Sheet
AD9542
Rev. 0 | Page 35 of 61
CAL_COUNT =
CAL_COUNT + 1
CAL_COUNT = 0
VCO
CALIBRATION
OPERATION
CAL_COUNT > 1
NO
YES
SYSTEM CLOCK
RECALIBRATION LOOP
WRITE:
REGISTER 0x2000[2] = 0
WRITE:
REGISTER 0x000F = 0x01
WRITE:
REGISTER 0x000F = 0x01
WRITE:
REGISTER 0x2000[2] = 1
START TIMEOUT CLOCK:
TIME = 0
REGISTER 0x3001[1:0] = 0x3
TIMEOUT CLOCK:
TIME > SYSCLK_TO1
NO
YES
NO
YES
SYSTEM CLOCK
LOCKED AND
STABLE POLLING LOOP
END
(TO RST_COUNT CHECK)
END
START
1SYSCLK_TO IS A CALCULATED TIME OUT VALUE.
IT IS 50ms + SYSTEM CLOCK VALIDATION TIME (REGISTER 0x0207 TO REGISTER 0x0209 [UNITS OF ms])
Figure 44. System Clock Initialization Subprocess



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