AD9542BCPZ datasheet(47/61 Pages) AD

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Data Sheet

AD9542

Rev. 0 | Page 47 of 61

The frequency lock detector provides the user with two status

bits in the IRQ map DPLLx mask section of the register map. The

DPLLx frequency lock bit (where x is 0 or 1) latches to Logic 1

when the DPLL changes state from not frequency locked to

frequency locked. The DPLLx frequency unlock bit latches to

Logic 1 when the DPLL changes state from frequency locked to

not frequency locked. Because these are latched bits, the user

must clear them via the IRQ map DPLLx clear section of the

of the frequency lock detector.

The frequency lock detector uses the 24-bit unsigned Profile x

frequency lock threshold bit field (where x is a value from 0

through 7, corresponding to a particular source profile),

specified in units of picoseconds. Thus, the frequency threshold

value extends from 0 ps to 16.7 µs and represents the absolute

value of the difference in period between the reference and

feedback signals at the input to the DPLL.

Profile x Frequency Lock Threshold = |1/f

REF − 1/fFB|/10

−12

where:

REF is the frequency of the signal at the DPLL PFD reference

input.

FB is the frequency of the signal at the DPLL PFD feedback

input.

Consider a case where it is desirable to set the Profile x

frequency lock threshold bit field to meet the frequency

threshold when the signal from the reference TDC is 80 kHz

and the signal from the feedback TDC is 79.32 kHz (or vice

versa).

Profile x Frequency Lock Threshold = |1/f

REF − 1/fFB|/10

−12

= |1/80,000 − 1/79,320|/10

−12

= 170,161 (nearest integer)

= 0x0298B1 (hexadecimal)

For more information on how to choose the appropriate frequency

lock threshold, fill rate, and drain rate values for a given application,

refer to the AN-1061 Application Note.

AD9542BCPZ Datasheet(PDF) 47 Page - Analog Devices

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