AD9542BCPZ datasheet(13/61 Pages) AD

13 / 61 page

Data Sheet

AD9542

Rev. 0 | Page 13 of 61

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SCLK

Clock Rate, 1/t

CLK

MHz

Pulse Width High, t

HIGH

Pulse Width Low, t

LOW

SDIO to SCLK Setup, t

2.2

SCLK to SDIO Hold, t

SCLK to Valid SDIO and SDO, t

CSB to SCLK Setup, t

1.5

CSB to SCLK Hold, t

CSB Minimum Pulse Width High

CLK

2C Mode

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUTS)

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

Input Logic 1 Voltage

% of VDDIOA

Input Logic 0 Voltage

0.3 ×

VDDIOA

Input Current

−10

+10

µA

For V

IN = 10% to 90% of VDDIOA

Hysteresis of Schmitt Trigger Inputs

1.5

% of VDDIOA

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.2

OUT = 3 mA

Output Fall Time from V

IH Minimum

to V

IL Maximum

20 + 0.1 × C

250

10 pF ≤ C

B ≤ 400 pF

TIMING

SCL Clock Rate

400

kHz

Bus Free Time Between a Stop and

Start Condition, t

BUF

1.3

µs

Repeated Start Condition Setup

Time, t

SU; STA

0.6

µs

Repeated Hold Time Start

Condition, t

HD; STA

0.6

µs

After this period, the first clock pulse is

generated

Stop Condition Setup Time, t

SU; STO

0.6

µs

Low Period of the SCL Clock, t

LOW

1.3

µs

High Period of the SCL Clock, t

HIGH

0.6

µs

SCL/SDA Rise Time, t

20 + 0.1 × C

300

SCL/SDA Fall Time, t

20 + 0.1 × C

300

Data Setup Time, t

SU; DAT

100

Data Hold Time, t

HD; DAT

100

Capacitive Load for Each Bus Line, C

400

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