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AD9542BCPZ Datasheet(PDF) 2 Page - Analog Devices

Part # AD9542BCPZ
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542BCPZ Datasheet(HTML) 2 Page - Analog Devices

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AD9542
Data Sheet
Rev. 0 | Page 2 of 61
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Supply Voltage............................................................................... 5
Supply Current.............................................................................. 5
Power Dissipation......................................................................... 5
System Clock Inputs, XOA and XOB......................................... 6
Reference Inputs ........................................................................... 7
Reference Monitors ...................................................................... 8
DPLL Phase Characteristics........................................................ 8
Distribution Clock Outputs ........................................................ 9
Time Duration of Digital Functions ........................................ 10
Digital PLL (DPLL0, DPLL1) Specifications .......................... 10
Digital PLL Lock Detection Specifications ............................. 11
Holdover Specifications............................................................. 11
Analog PLL (APLL0, APLL1) Specifications.......................... 11
Output Channel Divider Specifications .................................. 11
System Clock Compensation Specifications........................... 12
Temperature Sensor Specifications .......................................... 12
Serial Port Specifications ........................................................... 12
Logic Input Specifications (RESETB, M0 to M6) .................. 14
Logic Output Specifications (M0 to M6) ................................ 14
Jitter Generation (Random Jitter) ............................................ 14
Phase Noise ................................................................................. 15
Absolute Maximum Ratings.......................................................... 18
Thermal Resistance .................................................................... 18
ESD Caution................................................................................ 18
Pin Configuration and Function Descriptions........................... 19
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 25
Theory of Operation ...................................................................... 26
Overview...................................................................................... 26
Reference Input Physical Connections.................................... 26
Input/Output Termination Recommendations .......................... 27
System Clock Inputs................................................................... 27
Reference Clock Inputs.............................................................. 27
Clock Outputs ............................................................................. 28
System Clock PLL........................................................................... 29
System Clock Input Frequency Declaration ........................... 29
System Clock Source.................................................................. 29
2× Frequency Multiplier............................................................ 29
Prescale Divider.......................................................................... 29
Feedback Divider........................................................................ 30
System Clock PLL Output Frequency ..................................... 30
System Clock PLL Lock Detector............................................. 30
System Clock Stability Timer.................................................... 30
System Clock Input Termination Recommendations ........... 30
Digital PLL (DPLL) ........................................................................ 31
Overview ..................................................................................... 31
DPLL Phase/Frequency Lock Detectors ................................. 31
DPLL Loop Controller............................................................... 31
Applications Information .............................................................. 32
Optical Networking Line Card ................................................. 32
Small Cell Base Station .............................................................. 33
Initialization Sequence................................................................... 34
Status and Control Pins ................................................................. 37
Multifunction Pins at Reset/Power-Up ................................... 37
Status Functionality.................................................................... 38
Control Functionality ................................................................ 38
Interrupt Request (IRQ) ................................................................ 43
IRQ Monitor ............................................................................... 43
IRQ Mask..................................................................................... 43
IRQ Clear..................................................................................... 43
Watchdog Timer............................................................................. 45
Lock Detectors ................................................................................ 46
DPLL Lock Detectors ................................................................ 46
Phase Step Detector........................................................................ 48
Phase Step Limit ......................................................................... 48
Skew Adjustment........................................................................ 49
EEPROM Usage .............................................................................. 50
Overview ..................................................................................... 50
EEPROM Controller General Operation................................ 50
EEPROM Instruction Set .......................................................... 51
Multidevice Support................................................................... 53
Serial Control Port ......................................................................... 55
SPI/I²C Port Selection................................................................ 55
SPI Serial Port Operation .......................................................... 55



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