82801E datasheet(32/84 Pages) INTEL

32 / 84 page

Intel® 82801E C-ICH

Advance Information Datasheet

SDA[2:0]

Secondary IDE Device Address: These output signals are connected to the

corresponding signals on the secondary IDE connectors. They are used to

indicate which byte in either the ATA command block or control block is being

addressed.

SDCS1#

Secondary IDE Device Chip Selects for 100 Range: This signal is for the

ATA command register block. This output signal is connected to the

corresponding signal on the secondary IDE connector.

SDCS3#

Secondary IDE Device Chip Select for 300 Range: This signal is for the

ATA control register block. This output signal is connected to the

corresponding signal on the secondary IDE connector.

SDD[15:0]

I/O

Secondary IDE Device Data: These signals directly drive the corresponding

signals on the secondary IDE connector. There is a weak internal pull-down

resistor on SDD[7].

SDDACK#

Secondary IDE Device DMA Acknowledge: This signal directly drives the

DAK# signal on the secondary IDE connectors. This signal is asserted by the

82801E C-ICH to indicate to the IDE DMA slave device that a given data

transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.

This signal is used in conjunction with the PCI bus master IDE function and is

not associated with any AT-compatible DMA channel.

SDDREQ

Secondary IDE Device DMA Request: This input signal is directly driven

from the DRQ signals on the secondary IDE connector. It is asserted by the

IDE device to request a data transfer, and used in conjunction with the PCI

bus master IDE function. It is not associated with any AT-compatible DMA

channel. There is a weak internal pull-down resistor on SDDREQ.

SDIOR#

/(SDWSTB/

SRDMARDY#)

Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command

to the IDE device that it may drive data on the SDD lines. Data is latched by

the 82801E C-ICH on the deassertion edge of SDIOR#. The IDE device is

selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and

the SDA lines, or the IDE DMA acknowledge (SDDAK#).

Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data

write strobe for writes to disk. When writing to disk, the 82801E C-ICH drives

valid data on rising and falling edges of SDWSTB.

Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the

DMA ready for reads from disk. When reading from disk, the 82801E C-ICH

deasserts SRDMARDY# to pause burst data transfers.

SDIOW#

/(SDSTOP)

Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command

to the IDE device that it may latch data from the SDD lines. Data is latched by

the IDE device on the deassertion edge of SDIOW#. The IDE device is

selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and

the SDA lines, or the IDE DMA acknowledge (SDDAK#).

Secondary Disk Stop (Ultra DMA): The 82801E C-ICH asserts SDSTOP to

terminate a burst.

SERIRQ

I/O

Serial Interrupt Request: This pin implements the serial interrupt protocol.

SERR#

System Error: SERR# can be pulsed active by any PCI device that detects a

system error condition. Upon sampling SERR# active, the 82801E C-ICH has

the ability to generate an NMI, SMI#, or interrupt.

SIORDY

/(SDRSTB

/SWDMARDY#)

Secondary I/O Channel Ready (PIO): This signal keeps the strobe active

(SDIOR# on reads, SDIOW# on writes) longer than the minimum width. It

adds wait states to SIO transfers.

Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading

from disk, the 82801E C-ICH latches data from the disk on rising and falling

edges of SDRSTB.

Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to

disk, SWDMARDY# is deasserted by the disk to pause burst data transfers.

Table 6.

82801E C-ICH Signal Description (Sheet 8 of 11)

Signal

Type

Description

82801E Datasheet(PDF) 32 Page - Intel Corporation

82801E Datasheet(HTML) 32 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL