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82801E Datasheet(PDF) 35 Page - Intel Corporation |
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82801E Datasheet(HTML) 35 Page - Intel Corporation |
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35 / 84 page ![]() Intel® 82801E C-ICH Advance Information Datasheet 35 TRDY# I/O Target Ready: TRDY# indicates the 82801E C-ICH’s ability as a Target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the 82801E C-ICH, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the 82801E C-ICH, as a Target is prepared to latch data. TRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the Initiator and an output from the 82801E C-ICH when the 82801E C-ICH is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the 82801E C-ICH until driven by a target. UART_CLK I Input clock to the SIU. This clock is passed to the baud clock generation logic of each UART in the SIU. USBP0P USBP0N USBP1P USBP1N I/O Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. V5REF Reference for 5 V tolerance on Core well inputs. VBIAS RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. See “External RTC Circuitry” on page 50. Vcc1_8 1.8 V supply for Core well logic. Vcc3_3 3.3 V supply for Core well I/O buffers. VccRTC 3.3 V (can drop to 2.0 V minimum in the G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an 82801E C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. VRMPWRGD I VRM Power Good: This can be considered to be the CPU’s VRM power good. This signal should be ANDed with the ATX power supply’s PWROK signal. Vss Grounds. Table 6. 82801E C-ICH Signal Description (Sheet 11 of 11) Signal Type Description |
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