82801E datasheet(33/84 Pages) INTEL

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Intel® 82801E C-ICH

Advance Information Datasheet

SIU_LAD[3:0]

I/O

SIU LPC Multiplexed Command, Address, Data: Internal pull-ups are

provided.

SIU_LCLK

SIU LPC clock input to SIU: 33 MHz LPC clock.

SIU_LDRQ#

SIU LPC Serial DMA/Master Request Output: Used by SIU devices to

indicate a DMA request. These signals have weak internal pull-up resistors to

avoid external glue.

SIU_LFRAME#

SIU LPC Frame: Indicates the start of an LPC cycle, or an abort.

SIU_RESET#

SIU Reset: This signal should be tied to PCI RESET.

SIU_SERIRQ

I/O

SIU Serial IRQ input: This pin receives the serial interrupt protocol from

external devices. Pull up if unused.

SIU0_CTS#

SIU1_CTS#

Clear To Send: Active low, this pin indicates that data can be exchanged

between CICH and external interface. These pins have no effect on the

transmitter.

NOTE: These pins could be used as Modem Status Input whose condition

can be tested by the processor by reading bit 4 (CTS) of the Modem

Status register (MSR). Bit 4 is the complement of the CTS# signal.

Bit 0 (DCTS) of the MSR indicates whether the CTS# input has

changed state since the previous reading of the MSR. When the CTS

bit of the MSR changes state an interrupt is generated if the Modem

Status Interrupt is enabled.

SIU0_DCD#

SIU1_DCD#

Data Carrier Detect for UART0 and UART1: Active low, this pin indicates

that data carrier has been detected by the external agent.

NOTE: These pins are Modem Status Inputs whose condition can be tested

by the processor by reading bit 7 (DCD) of the Modem Status register

(MSR). Bit 7 is the complement of the DCD# signal. Bit 3 (DDCD) of

the MSR indicates whether the DCD# input has changed state since

the previous reading of the MSR. When the DCD bit of the MSR

changes state an interrupt is generated if the Modem Status Interrupt

is enabled.

SIU0_DSR#

SIU1_DSR#

Data Set Ready for UART0 and UART1: Active low, this pin indicates that

the external agent is ready to communicate with 82801E C-ICH UARTs.

These pins have no effect on the transmitter.

NOTE: These pins could be used as Modem Status Inputs whose condition

can be tested by the processor by reading bit 5 (DSR) of the Modem

Status register. Bit 5 is the complement of the DSR# signal. Bit 1

(DDSR) of the Modem status register (MSR) indicates whether the

DSR# input has changed state since the previous reading of the

MSR. When the DSR bit of the MSR changes state an interrupt is

generated if the Modem Status Interrupt is enabled.

SIU0_DTR#

SIU1_DTR#

Data Terminal Ready for UART0 and UART1: When low these pins informs

the modem or data set that CICH UART 0, 1 are ready to establish a

communication link. The DTR#x(x=0,1) output signals can be set to an active

low by programming the DTRx (x-0,1) (bit0) of the Modem control register to a

logic ‘1’. A Reset operation sets this signal to its inactive state (logic ‘1’).

LOOP mode operation holds this signal in its inactive state.

SIU0_RI#

SIU1_RI#

Ring Indicator for UART0 and UART1: Active low, this pin indicates that a

telephone ringing signal has been received by the external agent.

NOTE: These pins are Modem Status Input whose condition can be tested

by the processor by reading bit 6 (RI) of the Modem Status register

(MSR). Bit 6 is the complement of the RI# signal. Bit 2 (TERI) of the

MSR indicates whether the DCD# input has changed state since the

previous reading of the MSR. When the RI bit of the MSR changes

state an interrupt is generated if the Modem Status Interrupt is

enabled.

Table 6.

82801E C-ICH Signal Description (Sheet 9 of 11)

Signal

Type

Description

82801E Datasheet(PDF) 33 Page - Intel Corporation

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