HD64F2145 datasheet(147/829 Pages) RENESAS

147 / 829 page

Rev. 2.0, 08/02, page 107 of 788

Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

handling.

Table 5.7 shows the interrupt factor clear control and selection of interrupt factors by specification

of the DTCE bit of DTC's DTCERA to DTCERH, and the DISEL bit of DTC's MRB.

Table 5.7

Interrupt Source Selection and Clearing Control

Settings

DTC

Interrupt Sources Selection/Clearing Control

DTCE

DISEL

DTC

CPU

Legend

The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

The relevant interrupt is used. The interrupt source is not cleared.

×:

The relevant interrupt cannot be used.

Don’t care

Note:

The SCI, IIC, LPC, or A/D converter interrupt source is cleared when the DTC reads or

writes to the prescribed register, and is not dependent upon the DISEL bit.

5.7

Address Break

5.7.1

Features

This LSI can determine the specific address prefetch by the CPU to generate an address break

interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address

break interrupt exception handling is performed.

With this function, the execution start point of a program containing a bug is detected and

execution is branched to the correcting program.

HD64F2145 Datasheet(PDF) 147 Page - Renesas Technology Corp