HD64F2145 datasheet(153/829 Pages) RENESAS

153 / 829 page

Rev. 2.0, 08/02, page 113 of 788

Section 6 Bus Controller (BSC)

This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of

access states of the external address space. The BSC also has a bus arbitration function, and

controls the operation of the internal bus masters – CPU, and data transfer controller (DTC).

6.1

Features

• Basic bus interface

2-state access or 3-state access can be selected for each area

Program wait states can be inserted for each area

• Burst ROM interface

A burst ROM interface can be set for basic expansion areas

1-state access or 2-state access can be selected for burst access

• Idle cycle insertion

An idle cycle can be inserted for external write cycles immediately after external read cycles

• Bus arbitration function

Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC

Bus

controller

External bus control signals

Internal control signals

Wait

controller

BCR

WSCR

Bus mode signal

Bus arbiter

DTC bus acknowledge signal

CPU bus acknowledge signal

DTC bus request signal

CPU bus request signal

Figure 6.1 Block Diagram of Bus Controller

BSCS20AA_000020020700

HD64F2145 Datasheet(PDF) 153 Page - Renesas Technology Corp