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HD64F2145 Datasheet(PDF) 154 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 154 Page - Renesas Technology Corp |
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154 / 829 page  Rev. 2.0, 08/02, page 114 of 788 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Symbol I/O Function $6 Output Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). ,26 Output I/O select signal (when the IOSE bit in SYSCR is set to 1). 5' Output Strobe signal indicating that the external address space is being read. +:5 Output Strobe signal indicating that the external address space is being written to, and the upper half (D15 to D8) of the data bus is enabled. /:5 Output Strobe signal indicating that the external address space is being written to, and the lower half (D7 to D0) of the data bus is enabled. :$,7 Input Wait request signal when accessing the external 3-state access space. 6.3 Register Descriptions The bus controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). • Bus control register (BCR) • Wait state control register (WSCR) |
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