HD64F2145 datasheet(270/829 Pages) RENESAS

270 / 829 page

Rev. 2.0, 08/02, page 230 of 788

10.3.2

PWM (D/A) Data Registers A and B (DADRA, DADRB)

DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since

DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register

(TEMP). For details, refer to section 10.4, Bus Master Interface.

• DADRA

Bit

Bit Name

Initial Value

R/W

Description

DA13

DA12

DA11

DA10

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

R/W

D/A Data 13 to 0

These bits set a digital value to be converted to an

analog value.

In each base cycle, the DACNT value is continually

compared with the DADR value to determine the duty

cycle of the output waveform, and to decide whether to

output a fine-adjustment pulse equal in width to the

resolution. To enable this operation, this register must

be set within a range that depends on the CFS bit. If the

DADR value is outside this range, the PWM output is

held constant.

A channel can be operated with 12-bit precision by

keeping the two lowest data bits (DA1 and DA0) cleared

to 0. The two lowest data bits correspond to the two

highest bits in DACNT.

CFS

R/W

Carrier Frequency Select

0: Base cycle = resolution (T)

× 64

DADR range = H'0401 to H'FFFD

1: Base cycle = resolution (T)

× 256

DADR range = H'0103 to H'FFFF

0—

Reserved

This bit is always read as 1 and cannot be modified.

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