HD64F2145 datasheet(268/829 Pages) RENESAS

268 / 829 page

Rev. 2.0, 08/02, page 228 of 788

10.2

Input/Output Pins

Table 10.1 lists the PWM (D/A) module input and output pins.

Table 10.1

Pin Configuration

Name

Abbreviation

I/O

Function

PWM output pin X0

PWX0

Output

PWM output of PWMX channel A

PWM output pin X1

PWX1

Output

PWM output of PWMX channel B

10.3

The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the

same addresses with other registers. The registers are selected by the IICE bit in the serial timer

control register (STCR). For details on STCR, see section 3.2.3, Serial Timer Control Register

(STCR).

• PWM (D/A) counter H (DACNTH)

• PWM (D/A) counter L (DACNTL)

• PWM (D/A) data register AH (DADRAH)

• PWM (D/A) data register AL (DADRAL)

• PWM (D/A) data register BH (DADRBH)

• PWM (D/A) data register BL (DADRBL)

• PWM (D/A) control register (DACR)

Note:

The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.

Switching is performed by the REGS bit in DACNT or DADRB.

10.3.1

PWM (D/A) Counters H and L (DACNTH, DACNTL)

DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit

(CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a

channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-

bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of

16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details,

refer to section 10.4, Bus Master Interface.

HD64F2145 Datasheet(PDF) 268 Page - Renesas Technology Corp