TMS320F28375DPZP datasheet(59/222 Pages) TI1

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TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

www.ti.com

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9

System

5.9.1

Power Sequencing

5.9.1.1

Signal Pin Requirements

Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin,

and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).

5.9.1.2

VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements

The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional

operation.

5.9.1.3

VDD Requirements

The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source

used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.

VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when

VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC

Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core

Delfino™ MCUs Silicon Errata.

There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When

the flash banks are active and the device is in a low-activity state (for example, a low-power mode), this

internal current source can cause VDD to rise to approximately 1.3 V. There will be zero current load to the

external system VDD regulator while in this condition. This is not an issue for most regulators; however, if

the system voltage regulator requires a minimum load for proper operation, then an external 82Ω resistor

can be added to the board to ensure a minimal current load on VDD. See the "Low-Power Modes: Power

Down Flash or Maintain Minimum Device Activity" advisory in the TMS320F2837xD Dual-Core Delfino™

MCUs Silicon Errata.

5.9.1.4

Supply Ramp Rate

The supplies should ramp to full rail within 10 ms. Table 5-3 shows the supply ramp rate.

Table 5-3. Supply Ramp Rate

MIN

MAX

UNIT

Supply ramp rate

VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS

330

105

V/s

5.9.1.5

Supply Supervision

An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up.

External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails

and drive XRS low when supplies are outside operational specifications.

5.9.2

Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in

power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI

watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.

A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should

be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These

values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the

watchdog reset is asserted. Figure 5-4 shows the recommended reset circuit.

TMS320F28375DPZP Datasheet(PDF) 59 Page - Texas Instruments

TMS320F28375DPZP Datasheet(HTML) 59 Page - Texas Instruments

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