TMS320F28375DPZP datasheet(79/222 Pages) TI1

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WAKE

(A)

XCLKOUT

Address/Data

(internal)

w(WAKE)

d(WAKE-IDLE)

TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

www.ti.com

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9.8.3

Low-Power Mode Wakeup Timing

Table 5-29 shows the IDLE mode timing requirements, Table 5-30 shows the switching characteristics,

and Figure 5-17 shows the timing diagram for IDLE mode.

(1)

For an explanation of the input qualifier parameters, see Table 5-24.

Table 5-29. IDLE Mode Timing Requirements(1)

MIN

MAX

UNIT

tw(WAKE)

Pulse duration, external wake-up signal

Without input qualifier

2tc(SYSCLK)

cycles

With input qualifier

2tc(SYSCLK) + tw(IQSW)

(1)

For an explanation of the input qualifier parameters, see Table 5-24.

(2)

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

(3)

This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and

FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD

Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3,

and FPAC1[PSLEEP] is 0x860.

Table 5-30. IDLE Mode Switching Characteristics(1)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td(WAKE-IDLE)

Delay time, external wake signal to program execution resume (2)

cycles

•

Wakeup from Flash

–

Flash module in active state

Without input qualifier

40tc(SYSCLK)

With input qualifier

40tc(SYSCLK) + tw(WAKE)

•

Wakeup from Flash

–

Flash module in sleep state

Without input qualifier

6700tc(SYSCLK)

(3)

With input qualifier

6700tc(SYSCLK)

(3) + t

w(WAKE)

•

Wakeup from RAM

Without input qualifier

25tc(SYSCLK)

With input qualifier

25tc(SYSCLK) + tw(WAKE)

WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK

cycles (minimum) is needed before the wake-up signal could be asserted.

Figure 5-17. IDLE Entry and Exit Timing Diagram

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