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TMS320F28375DPZP Datasheet(PDF) 82 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 222 page ![]() 82 TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Specifications Copyright © 2013–2018, Texas Instruments Incorporated Table 5-33 shows the HALT mode timing requirements, Table 5-34 shows the switching characteristics, and Figure 5-19 shows the timing diagram for HALT mode. (1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/layout external to the device. See Table 5-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see Section 5.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device. Table 5-33. HALT Mode Timing Requirements MIN MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles (1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860. Table 5-34. HALT Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles td(WAKE-HALT) Delay time, external wake signal end to CPU1 program execution resume cycles • Wakeup from flash – Flash module in active state 75tc(OSCCLK) • Wakeup from flash – Flash module in sleep state 17500tc(OSCCLK) (1) • Wakeup from RAM 75tc(OSCCLK) |
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