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TMS320F28375DPZP Datasheet(PDF) 76 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 76 Page - Texas Instruments |
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76 / 222 page ![]() INPUTXBAR4 CPU1.W DINT CPU2.W DINT CPU1.LPMINT CPU2 .LPMINT CPU1.W AKEINT CPU2.W AKEINT CPU1.TINT0 CPU1. ePIE IN T13 INT14 NMI CPU1 INT1 to INT12 NMI CPU2 INT1 to INT12 INPUTXBAR13 INPUTXBAR5 INPUTXBAR6 INPUTXBAR14 GPIO0 GPIO1 ... ... GPIOx CPU1.TIMER0 CPU2.TINT0 CPU2.TIMER0 CPU2 ePIE CPU1.TINT1 CPU1.TIMER1 CPU1.TINT2 CPU1.TIMER2 CPU1.TINT2 IN T13 INT14 CPU2.TINT1 CPU2.TIMER1 CPU2.TINT2 CPU2.TIMER2 LPM Logic CPU2.WD Peripherals IPC 4 Interrupts CPU1.XINT1 Control CPU1.XINT5 Control CPU1.XINT3 Control CPU1.XINT4 Control CPU1.XINT2 Control CPU2.XINT1 Control CPU2.XINT5 Control CPU2.XINT3 Control CPU2.XINT4 Control CPU2.XINT2 Control Input X-BAR LPM Logic CPU1.WD CPU1.NMIWD CPU2.NMIWD 76 TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Specifications Copyright © 2013–2018, Texas Instruments Incorporated 5.9.7 Interrupts Figure 5-15 provides a high-level view of the interrupt architecture. As shown in Figure 5-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins. In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group. Figure 5-15. External and ePIE Interrupt Sources |
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