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TMS320F28375DPZP Datasheet(PDF) 89 Page - Texas Instruments

Part # TMS320F28375DPZP
Description  TMS320F2837xD Dual-Core Delfino??Microcontrollers
PDF  222 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320F28375DPZP Datasheet(HTML) 89 Page - Texas Instruments

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TMS320F28379D, TMS320F28378D, TMS320F28377D
TMS320F28376D, TMS320F28375D, TMS320F28374D
www.ti.com
SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018
Submit Documentation Feedback
Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D
TMS320F28374D
Specifications
Copyright © 2013–2018, Texas Instruments Incorporated
Table 5-38. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO.
PARAMETER
MIN
MAX
UNIT
8
tsu(EMAV-EMOEL)
Output setup time, EMxA[y:0] valid
to EMxOE low
(RS)*E–3
(RS)*E+2
ns
9
th(EMOEH-EMAIV)
Output hold time, EMxOE high to
EMxA[y:0] invalid
(RH)*E–3
(RH)*E
ns
10
tw(EMOEL)
EMxOE active low width (EW = 0)
(RST)*E–1
(RST)*E+1
ns
EMxOE active low width (EW = 1)
(RST+(EWC*16))*E–1
(RST+(EWC*16))*E+1
ns
11
td(EMWAITH-EMOEH)
Delay time from EMxWAIT
deasserted to EMxOE high
4E+10
5E+15
ns
29
tsu(EMDQMV-EMOEL)
Output setup time, EMxDQM[y:0]
valid to EMxOE low
(RS)*E–3
(RS)*E+2
ns
30
th(EMOEH-EMDQMIV)
Output hold time, EMxOE high to
EMxDQM[y:0] invalid
(RH)*E–3
(RH)*E
ns
Writes
15
tc(EMWCYCLE)
EMIF write cycle time (EW = 0)
(WS+WST+WH+2)*E–3
(WS+WST+WH+2)*E+1
ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+2+
(EWC*16))*E–3
(WS+WST+WH+2+
(EWC*16))*E+1
ns
16
tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 0)
(WS)*E–3
(WS)*E+1
ns
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 1)
–3
1
ns
17
th(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0)
(WH)*E–3
(WH)*E
ns
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1)
–3
0
ns
18
tsu(EMDQMV-EMWEL)
Output setup time, EMxDQM[y:0]
valid to EMxWE low
(WS)*E–3
(WS)*E+1
ns
19
th(EMWEH-EMDQMIV)
Output hold time, EMxWE high to
EMxDQM[y:0] invalid
(WH)*E–3
(WH)*E
ns
20
tsu(EMBAV-EMWEL)
Output setup time, EMxBA[y:0]
valid to EMxWE low
(WS)*E–3
(WS)*E+1
ns
21
th(EMWEH-EMBAIV)
Output hold time, EMxWE high to
EMxBA[y:0] invalid
(WH)*E–3
(WH)*E
ns
22
tsu(EMAV-EMWEL)
Output setup time, EMxA[y:0] valid
to EMxWE low
(WS)*E–3
(WS)*E+1
ns
23
th(EMWEH-EMAIV)
Output hold time, EMxWE high to
EMxA[y:0] invalid
(WH)*E–3
(WH)*E
ns
24
tw(EMWEL)
EMxWE active low width
(EW = 0)
(WST)*E–1
(WST)*E+1
ns
EMxWE active low width
(EW = 1)
(WST+(EWC*16))*E–1
(WST+(EWC*16))*E+1
ns
25
td(EMWAITH-EMWEH)
Delay time from EMxWAIT
deasserted to EMxWE high
4E+10
5E+15
ns
26
tsu(EMDV-EMWEL)
Output setup time, EMxD[y:0] valid
to EMxWE low
(WS)*E–3
(WS)*E+1
ns
27
th(EMWEH-EMDIV)
Output hold time, EMxWE high to
EMxD[y:0] invalid
(WH)*E–3
(WH)*E
ns



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