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TMS320F28375DPZP Datasheet(PDF) 60 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 222 page ![]() XRS £100 nF 2.2 k – 10 k W W V DDIO 60 TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Specifications Copyright © 2013–2018, Texas Instruments Incorporated Figure 5-4. Reset Circuit 5.9.2.1 Reset Sources The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. The parameter th(boot-mode) must account for a reset initiated from any of these sources. CAUTION Some reset sources are internally driven by the device. Some of these sources will drive XRS low. Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by other devices in the system. The boot configuration has a provision for changing the boot pins in OTP; for more details, see the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. 5.9.2.2 Reset Electrical Data and Timing Table 5-4 shows the reset (XRS) timing requirements. Table 5-5 shows the reset (XRS) switching characteristics. Figure 5-5 shows the power-on reset. Figure 5-6 shows the warm reset. Table 5-4. Reset (XRS) Timing Requirements MIN MAX UNIT th(boot-mode) Hold time for boot-mode pins 1.5 ms tw(RSL2) Pulse duration, XRS low on warm reset 3.2 µs Table 5-5. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven low by device after supplies are stable 100 µs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles |
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