TMS320F28375DPZP datasheet(87/222 Pages) TI1

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TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

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SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9.9

External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous

memories (SRAM, NOR flash) or synchronous memory (SDRAM).

5.9.9.1

Asynchronous Memory Support

The EMIF supports asynchronous memories:

•

SRAMs

•

NOR Flash memories

There is an external wait input that allows slower asynchronous memories to extend the memory access.

The EMIF module supports up to three chip selects (EMIF_CS[4:2]). Each chip select has the following

individually programmable attributes:

•

Data bus width

•

Read cycle timings: setup, hold, strobe

•

Write cycle timings: setup, hold, strobe

•

Bus turnaround time

•

Extended wait option with programmable time-out

•

Select strobe option

5.9.9.2

Synchronous DRAM Support

The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit

data bus. The EMIF has a single SDRAM chip select (EMIF_CS[0]).

The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of

the program address bus and can only be accessed through the data bus, which places a restriction on

the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the

user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the

examples in C2000Ware (C2000Ware for C2000 MCUs) and the TMS320F2837xD Dual-Core Delfino

Microcontrollers Technical Reference Manual.

SDRAM configurations supported are:

•

One-bank, two-bank, and four-bank SDRAM devices

•

Devices with 8-, 9-, 10-, and 11-column addresses

•

CAS latency of two or three clock cycles

•

16-bit/32-bit data bus width

•

3.3-V LVCMOS interface

Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh

mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the

SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode

achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if

data retention is required. The EMIF module does not support mobile SDRAM devices.

On this device, the EMIF does not support burst access for SDRAM configurations. This means every

access to an external SDRAM device will have CAS latency.

TMS320F28375DPZP Datasheet(PDF) 87 Page - Texas Instruments

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