TMS320F28375DPZP datasheet(64/222 Pages) TI1

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TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9.3.2

Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times,

frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.

5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times

Table 5-7 shows the frequency requirements for the input clocks. Table 5-16 shows the crystal equivalent

series resistance requirements. Table 5-8 shows the X1 input level characteristics when using an external

clock source. Table 5-9 and Table 5-10 show the timing requirements for the input clocks. Table 5-11

shows the PLL lock times for the Main PLL and the USB PLL.

Table 5-7. Input Clock Frequency

MIN

MAX

UNIT

f(XTAL)

Frequency, X1/X2, from external crystal or resonator

MHz

f(X1)

Frequency, X1, from external oscillator (PLL enabled)

MHz

Frequency, X1, from external oscillator (PLL disabled)

100

MHz

f(AUXI)

Frequency, AUXCLKIN, from external oscillator

MHz

Table 5-8. X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

X1 VIL

Valid low-level input voltage

–0.3

0.3 * VDDIO

X1 VIH

Valid high-level input voltage

0.7 * VDDIO

VDDIO + 0.3

Table 5-9. X1 Timing Requirements

MIN

MAX

UNIT

tf(X1)

Fall time, X1

tr(X1)

Rise time, X1

tw(X1L)

Pulse duration, X1 low as a percentage of tc(X1)

45%

55%

tw(X1H)

Pulse duration, X1 high as a percentage of tc(X1)

45%

55%

Table 5-10. AUXCLKIN Timing Requirements

MIN

MAX

UNIT

tf(AUXI)

Fall time, AUXCLKIN

tr(AUXI)

Rise time, AUXCLKIN

tw(AUXL)

Pulse duration, AUXCLKIN low as a percentage of tc(XCI)

45%

55%

tw(AUXH)

Pulse duration, AUXCLKIN high as a percentage of tc(XCI)

45%

55%

(1)

The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2837xD Dual-Core

Delfino™ MCUs Silicon Errata. Cycle count includes code execution of the PLL initialization routine, which could vary depending on

compiler optimizations and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs.

For the system PLL, see InitSysPll() or SysCtl_setClock(). For the auxillary PLL, see InitAuxPll() or SysCtl_setAuxClock().

Table 5-11. PLL Lock Times

MIN

NOM

MAX

UNIT

t(PLL)

Lock time, Main PLL (X1, from external oscillator)

50 µs + 2500 * tc(OSCCLK)

(1)

µs

t(USB)

Lock time, USB PLL (AUXCLKIN, from external oscillator)

50 µs + 2500 * tc(OSCCLK)

(1)

µs

TMS320F28375DPZP Datasheet(PDF) 64 Page - Texas Instruments

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