TMS320F28375DPZP datasheet(83/222 Pages) TI1

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OSCCLK

XCLKOUT

HALT

Flushing Pipeline

Device

Status

Normal

Execution

GPIOn

(A)

(C)

(D)(E)

(F)

(B)

(G)

d(IDLE-XCOS)

w(WAKE-GPIO)

d(WAKE-HALT)

Oscillator Start-up Time

TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

www.ti.com

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D

TMS320F28374D

Specifications

IDLE instruction is executed to put the device into HALT mode.

The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being

turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.

Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as

the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very

little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in

HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay

of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator

wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables

the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin

asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to

entering and during HALT mode.

The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.

When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The

HALT mode is now exited.

Normal operation resumes.

The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 5-19. HALT Entry and Exit Timing Diagram

NOTE

CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should

verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the

IDLE instruction to enter HALT.

TMS320F28375DPZP Datasheet(PDF) 83 Page - Texas Instruments

TMS320F28375DPZP Datasheet(HTML) 83 Page - Texas Instruments

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