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TMS320F28375DPZP Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 222 page  Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 TMS320F2837xD Dual-Core Delfino™ Microcontrollers 1 Device Overview 1 1.1 Features 1 • Dual-Core Architecture – Two TMS320C28x 32-Bit CPUs – 200 MHz – IEEE 754 Single-Precision Floating-Point Unit (FPU) – Trigonometric Math Unit (TMU) – Viterbi/Complex Math Unit (VCU-II) • Two Programmable Control Law Accelerators (CLAs) – 200 MHz – IEEE 754 Single-Precision Floating-Point Instructions – Executes Code Independently of Main CPU • On-Chip Memory – 512KB (256KW) or 1MB (512KW) of Flash (ECC-Protected) – 172KB (86KW) or 204KB (102KW) of RAM (ECC-Protected or Parity-Protected) – Dual-Zone Security Supporting Third-Party Development – Unique Identification Number • Clock and System Control – Two Internal Zero-Pin 10-MHz Oscillators – On-Chip Crystal Oscillator – Windowed Watchdog Timer Module – Missing Clock Detection Circuitry • 1.2-V Core, 3.3-V I/O Design • System Peripherals – Two External Memory Interfaces (EMIFs) With ASRAM and SDRAM Support – Dual 6-Channel Direct Memory Access (DMA) Controllers – Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering – Expanded Peripheral Interrupt Controller (ePIE) – Multiple Low-Power Mode (LPM) Support With External Wakeup • Communications Peripherals – USB 2.0 (MAC + PHY) – Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface – Two Controller Area Network (CAN) Modules (Pin-Bootable) – Three High-Speed (up to 50-MHz) SPI Ports (Pin-Bootable) – Two Multichannel Buffered Serial Ports (McBSPs) – Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable) – Two I2C Interfaces (Pin-Bootable) • Analog Subsystem – Up to Four Analog-to-Digital Converters (ADCs) – 16-Bit Mode – 1.1 MSPS Each (up to 4.4-MSPS System Throughput) – Differential Inputs – Up to 12 External Channels – 12-Bit Mode – 3.5 MSPS Each (up to 14-MSPS System Throughput) – Single-Ended Inputs – Up to 24 External Channels – Single Sample-and-Hold (S/H) on Each ADC – Hardware-Integrated Post-Processing of ADC Conversions – Saturating Offset Calibration – Error From Setpoint Calculation – High, Low, and Zero-Crossing Compare, With Interrupt Capability – Trigger-to-Sample Delay Capture – Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References – Three 12-Bit Buffered DAC Outputs • Enhanced Control Peripherals – 24 Pulse Width Modulator (PWM) Channels With Enhanced Features – 16 High-Resolution Pulse Width Modulator (HRPWM) Channels – High Resolution on Both A and B Channels of 8 PWM Modules – Dead-Band Support (on Both Standard and High Resolution) – Six Enhanced Capture (eCAP) Modules – Three Enhanced Quadrature Encoder Pulse (eQEP) Modules – Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel – Standard SDFM Data Filtering – Comparator Filter for Fast Action for Out of Range |
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