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TMS320F28375DPZP Datasheet(PDF) 78 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 222 page  78 TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Specifications Copyright © 2013–2018, Texas Instruments Incorporated 5.9.8 Low-Power Modes This device has three clock-gating low-power modes and a special power-gating mode. Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. 5.9.8.1 Clock-Gating Low-Power Modes IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 5-27 describes the effect on the system when any of the clock-gating low-power modes are entered. Table 5-27. Effect of Clock-Gating Low-Power Modes on the Device MODULES/ CLOCK DOMAIN CPU1 IDLE CPU1 STANDBY CPU2 IDLE CPU2 STANDBY HALT CPU1.CLKIN Active Gated N/A N/A Gated CPU1.SYSCLK Active Gated N/A N/A Gated CPU1.CPUCLK Gated Gated N/A N/A Gated CPU2.CLKIN N/A N/A Active Gated Gated CPU2.SYSCLK N/A N/A Active Gated Gated CPU2.CPUCLK N/A N/A Gated Gated Gated Clock to modules Connected to PERx.SYSCLK Active Gated if CPUSEL.PERx = CPU1 Active Gated if CPUSEL.PERx = CPU2 Gated CPU1.WDCLK Active Active N/A N/A Gated if CLKSRCCTL1.WDHALTI = 0 CPU2.WDCLK N/A N/A Active Active Gated AUXPLLCLK Active Active Active Active Gated PLL Powered Powered Powered Powered Software must power down PLL before entering HALT INTOSC1 Powered Powered Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0 INTOSC2 Powered Powered Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0 Flash Powered Powered Powered Powered Software-Controlled X1/X2 Crystal Oscillator Powered Powered Powered Powered Powered-Down 5.9.8.2 Power-Gating Low-Power Modes HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup capability, and can be used to save power during long periods of inactivity. Table 5-28 describes the effects on the system when the HIBERNATE mode is entered. Table 5-28. Effect of Power-Gating Low-Power Mode on the Device MODULES/POWER DOMAINS HIBERNATE M0 and M1 memories ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00 ● Are off when LPMCR.M0M1MODE = 0x01 CPU1, CPU2, digital peripherals Powered down Dx, LSx, GSx memories Power down, memory contents are lost I/Os On with output state preserved Oscillators, PLL, analog peripherals, Flash Enters Low-Power Mode |
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