TMS320F28375DPZP datasheet(74/222 Pages) TI1

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GPIO Signal

Sampling Window

SYSCLK

(A)

GPxQSELn = 1,0 (6 samples)

(D)

Output From

Qualifier

QUALPRD = 1

(SYSCLK/2)

w(IQSW)

w(SP)

(SYSCLK cycle * 2 * QUALPRD) * 5

(C)

Sampling Period determined

by GPxCTRL[QUALPRD]

(B)

TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9.6.2

GPIO - Input Timing

Table 5-24 shows the general-purpose input timing requirements. Figure 5-13 shows the sampling mode.

(1)

"n" represents the number of qualification samples as defined by GPxQSELn register.

(2)

For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

Table 5-24. General-Purpose Input Timing Requirements

MIN

MAX

UNIT

tw(SP)

Sampling period

QUALPRD = 0

1tc(SYSCLK)

cycles

QUALPRD

≠ 0

2tc(SYSCLK) * QUALPRD

cycles

tw(IQSW)

Input qualifier sampling window

tw(SP) * (n

(1) – 1)

cycles

tw(GPI)

(2)

Pulse duration, GPIO low/high

Synchronous mode

2tc(SYSCLK)

cycles

With input qualifier

tw(IQSW) + tw(SP) + 1tc(SYSCLK)

cycles

This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It

can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n",

the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be

sampled).

The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.

The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is

used.

In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or

greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure

5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide

pulse ensures reliable recognition.

Figure 5-13. Sampling Mode

TMS320F28375DPZP Datasheet(PDF) 74 Page - Texas Instruments

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