AX58200 datasheet(87/180 Pages) ASIX

87 / 180 page

AX58200

EtherCAT Slave Controller SoC

External Bus Interface (EBI)

2.30.1 Overview

This chip is equipped with an external bus interface (EBI) for external device use. To save the connections

between an external device and a chip, EBI is operating at address bus and data bus multiplex mode. The EBI

supports three chip selects that can connect three external devices with different timing setting requirements.

2.30.2 Features

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Supports up to three memory banks

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Supports dedicated external chip select pin with polarity control for each bank

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Supports accessible space up to 1 Mbytes for each bank, actually external addressable space is

dependent on package pin out

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Supports 8-/16-bit data width

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Supports byte write in 16-bit data width mode

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Supports Address/Data multiplexed Mode

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Supports Timing parameters individual adjustment for each memory block

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Supports LCD interface i80 mode

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Supports PDMA mode

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Supports variable external bus base clock (MCLK) which based on HCLK

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Supports configurable idle cycle for different access condition: Idle of Write command finish

(W2X) and Idle of Read-to-Read (R2R)

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Supports address bus and data bus separate mode

AX58200 Datasheet(PDF) 87 Page - ASIX Electronics Corporation